// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  cfg_sche_reg_offset_field.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  Huawei
// Version       :  1
// Date          :  2016/06/10
// Description   :  The description of P680 project
// Others        :  Generated automatically by nManager V4.1 
// History       :  Huawei 2018/08/23 10:14:57 Create file
// ******************************************************************************

#ifndef __CFG_SCHE_REG_OFFSET_FIELD_H__
#define __CFG_SCHE_REG_OFFSET_FIELD_H__

#define CFG_SCHE_RESERVED_0_LEN             24
#define CFG_SCHE_RESERVED_0_OFFSET          8
#define CFG_SCHE_LONG_PKT_AR_CNT_CFG_LEN    8
#define CFG_SCHE_LONG_PKT_AR_CNT_CFG_OFFSET 0

#define CFG_SCHE_RESERVED_0_LEN             24
#define CFG_SCHE_RESERVED_0_OFFSET          8
#define CFG_SCHE_LONG_PKT_AW_CNT_CFG_LEN    8
#define CFG_SCHE_LONG_PKT_AW_CNT_CFG_OFFSET 0

#define CFG_SCHE_PORT7_ARQOS_SRC_SEL_LEN    4
#define CFG_SCHE_PORT7_ARQOS_SRC_SEL_OFFSET 28
#define CFG_SCHE_PORT6_ARQOS_SRC_SEL_LEN    4
#define CFG_SCHE_PORT6_ARQOS_SRC_SEL_OFFSET 24
#define CFG_SCHE_PORT5_ARQOS_SRC_SEL_LEN    4
#define CFG_SCHE_PORT5_ARQOS_SRC_SEL_OFFSET 20
#define CFG_SCHE_PORT4_ARQOS_SRC_SEL_LEN    4
#define CFG_SCHE_PORT4_ARQOS_SRC_SEL_OFFSET 16
#define CFG_SCHE_PORT3_ARQOS_SRC_SEL_LEN    4
#define CFG_SCHE_PORT3_ARQOS_SRC_SEL_OFFSET 12
#define CFG_SCHE_PORT2_ARQOS_SRC_SEL_LEN    4
#define CFG_SCHE_PORT2_ARQOS_SRC_SEL_OFFSET 8
#define CFG_SCHE_PORT1_ARQOS_SRC_SEL_LEN    4
#define CFG_SCHE_PORT1_ARQOS_SRC_SEL_OFFSET 4
#define CFG_SCHE_PORT0_ARQOS_SRC_SEL_LEN    4
#define CFG_SCHE_PORT0_ARQOS_SRC_SEL_OFFSET 0

#define CFG_SCHE_PORT7_AWQOS_SRC_SEL_LEN    4
#define CFG_SCHE_PORT7_AWQOS_SRC_SEL_OFFSET 28
#define CFG_SCHE_PORT6_AWQOS_SRC_SEL_LEN    4
#define CFG_SCHE_PORT6_AWQOS_SRC_SEL_OFFSET 24
#define CFG_SCHE_PORT5_AWQOS_SRC_SEL_LEN    4
#define CFG_SCHE_PORT5_AWQOS_SRC_SEL_OFFSET 20
#define CFG_SCHE_PORT4_AWQOS_SRC_SEL_LEN    4
#define CFG_SCHE_PORT4_AWQOS_SRC_SEL_OFFSET 16
#define CFG_SCHE_PORT3_AWQOS_SRC_SEL_LEN    4
#define CFG_SCHE_PORT3_AWQOS_SRC_SEL_OFFSET 12
#define CFG_SCHE_PORT2_AWQOS_SRC_SEL_LEN    4
#define CFG_SCHE_PORT2_AWQOS_SRC_SEL_OFFSET 8
#define CFG_SCHE_PORT1_AWQOS_SRC_SEL_LEN    4
#define CFG_SCHE_PORT1_AWQOS_SRC_SEL_OFFSET 4
#define CFG_SCHE_PORT0_AWQOS_SRC_SEL_LEN    4
#define CFG_SCHE_PORT0_AWQOS_SRC_SEL_OFFSET 0

#define CFG_SCHE_PORT7_AR_QOS_LEN    4
#define CFG_SCHE_PORT7_AR_QOS_OFFSET 28
#define CFG_SCHE_PORT6_AR_QOS_LEN    4
#define CFG_SCHE_PORT6_AR_QOS_OFFSET 24
#define CFG_SCHE_PORT5_AR_QOS_LEN    4
#define CFG_SCHE_PORT5_AR_QOS_OFFSET 20
#define CFG_SCHE_PORT4_AR_QOS_LEN    4
#define CFG_SCHE_PORT4_AR_QOS_OFFSET 16
#define CFG_SCHE_PORT3_AR_QOS_LEN    4
#define CFG_SCHE_PORT3_AR_QOS_OFFSET 12
#define CFG_SCHE_PORT2_AR_QOS_LEN    4
#define CFG_SCHE_PORT2_AR_QOS_OFFSET 8
#define CFG_SCHE_PORT1_AR_QOS_LEN    4
#define CFG_SCHE_PORT1_AR_QOS_OFFSET 4
#define CFG_SCHE_PORT0_AR_QOS_LEN    4
#define CFG_SCHE_PORT0_AR_QOS_OFFSET 0

#define CFG_SCHE_PORT7_AW_QOS_LEN    4
#define CFG_SCHE_PORT7_AW_QOS_OFFSET 28
#define CFG_SCHE_PORT6_AW_QOS_LEN    4
#define CFG_SCHE_PORT6_AW_QOS_OFFSET 24
#define CFG_SCHE_PORT5_AW_QOS_LEN    4
#define CFG_SCHE_PORT5_AW_QOS_OFFSET 20
#define CFG_SCHE_PORT4_AW_QOS_LEN    4
#define CFG_SCHE_PORT4_AW_QOS_OFFSET 16
#define CFG_SCHE_PORT3_AW_QOS_LEN    4
#define CFG_SCHE_PORT3_AW_QOS_OFFSET 12
#define CFG_SCHE_PORT2_AW_QOS_LEN    4
#define CFG_SCHE_PORT2_AW_QOS_OFFSET 8
#define CFG_SCHE_PORT1_AW_QOS_LEN    4
#define CFG_SCHE_PORT1_AW_QOS_OFFSET 4
#define CFG_SCHE_PORT0_AW_QOS_LEN    4
#define CFG_SCHE_PORT0_AW_QOS_OFFSET 0

#define CFG_SCHE_RESERVED_0_LEN         1
#define CFG_SCHE_RESERVED_0_OFFSET      31
#define CFG_SCHE_PORT3_AR_WEIGHT_LEN    7
#define CFG_SCHE_PORT3_AR_WEIGHT_OFFSET 24
#define CFG_SCHE_RESERVED_1_LEN         1
#define CFG_SCHE_RESERVED_1_OFFSET      23
#define CFG_SCHE_PORT2_AR_WEIGHT_LEN    7
#define CFG_SCHE_PORT2_AR_WEIGHT_OFFSET 16
#define CFG_SCHE_RESERVED_2_LEN         1
#define CFG_SCHE_RESERVED_2_OFFSET      15
#define CFG_SCHE_PORT1_AR_WEIGHT_LEN    7
#define CFG_SCHE_PORT1_AR_WEIGHT_OFFSET 8
#define CFG_SCHE_RESERVED_3_LEN         1
#define CFG_SCHE_RESERVED_3_OFFSET      7
#define CFG_SCHE_PORT0_AR_WEIGHT_LEN    7
#define CFG_SCHE_PORT0_AR_WEIGHT_OFFSET 0

#define CFG_SCHE_RESERVED_0_LEN         1
#define CFG_SCHE_RESERVED_0_OFFSET      31
#define CFG_SCHE_PORT7_AR_WEIGHT_LEN    7
#define CFG_SCHE_PORT7_AR_WEIGHT_OFFSET 24
#define CFG_SCHE_RESERVED_1_LEN         1
#define CFG_SCHE_RESERVED_1_OFFSET      23
#define CFG_SCHE_PORT6_AR_WEIGHT_LEN    7
#define CFG_SCHE_PORT6_AR_WEIGHT_OFFSET 16
#define CFG_SCHE_RESERVED_2_LEN         1
#define CFG_SCHE_RESERVED_2_OFFSET      15
#define CFG_SCHE_PORT5_AR_WEIGHT_LEN    7
#define CFG_SCHE_PORT5_AR_WEIGHT_OFFSET 8
#define CFG_SCHE_RESERVED_3_LEN         1
#define CFG_SCHE_RESERVED_3_OFFSET      7
#define CFG_SCHE_PORT4_AR_WEIGHT_LEN    7
#define CFG_SCHE_PORT4_AR_WEIGHT_OFFSET 0

#define CFG_SCHE_RESERVED_0_LEN         1
#define CFG_SCHE_RESERVED_0_OFFSET      31
#define CFG_SCHE_PORT3_AW_WEIGHT_LEN    7
#define CFG_SCHE_PORT3_AW_WEIGHT_OFFSET 24
#define CFG_SCHE_RESERVED_1_LEN         1
#define CFG_SCHE_RESERVED_1_OFFSET      23
#define CFG_SCHE_PORT2_AW_WEIGHT_LEN    7
#define CFG_SCHE_PORT2_AW_WEIGHT_OFFSET 16
#define CFG_SCHE_RESERVED_2_LEN         1
#define CFG_SCHE_RESERVED_2_OFFSET      15
#define CFG_SCHE_PORT1_AW_WEIGHT_LEN    7
#define CFG_SCHE_PORT1_AW_WEIGHT_OFFSET 8
#define CFG_SCHE_RESERVED_3_LEN         1
#define CFG_SCHE_RESERVED_3_OFFSET      7
#define CFG_SCHE_PORT0_AW_WEIGHT_LEN    7
#define CFG_SCHE_PORT0_AW_WEIGHT_OFFSET 0

#define CFG_SCHE_RESERVED_0_LEN         1
#define CFG_SCHE_RESERVED_0_OFFSET      31
#define CFG_SCHE_PORT7_AW_WEIGHT_LEN    7
#define CFG_SCHE_PORT7_AW_WEIGHT_OFFSET 24
#define CFG_SCHE_RESERVED_1_LEN         1
#define CFG_SCHE_RESERVED_1_OFFSET      23
#define CFG_SCHE_PORT6_AW_WEIGHT_LEN    7
#define CFG_SCHE_PORT6_AW_WEIGHT_OFFSET 16
#define CFG_SCHE_RESERVED_2_LEN         1
#define CFG_SCHE_RESERVED_2_OFFSET      15
#define CFG_SCHE_PORT5_AW_WEIGHT_LEN    7
#define CFG_SCHE_PORT5_AW_WEIGHT_OFFSET 8
#define CFG_SCHE_RESERVED_3_LEN         1
#define CFG_SCHE_RESERVED_3_OFFSET      7
#define CFG_SCHE_PORT4_AW_WEIGHT_LEN    7
#define CFG_SCHE_PORT4_AW_WEIGHT_OFFSET 0

#define CFG_SCHE_PORT3_AR_OSLMT_LEN    8
#define CFG_SCHE_PORT3_AR_OSLMT_OFFSET 24
#define CFG_SCHE_PORT2_AR_OSLMT_LEN    8
#define CFG_SCHE_PORT2_AR_OSLMT_OFFSET 16
#define CFG_SCHE_PORT1_AR_OSLMT_LEN    8
#define CFG_SCHE_PORT1_AR_OSLMT_OFFSET 8
#define CFG_SCHE_PORT0_AR_OSLMT_LEN    8
#define CFG_SCHE_PORT0_AR_OSLMT_OFFSET 0

#define CFG_SCHE_PORT7_AR_OSLMT_LEN    8
#define CFG_SCHE_PORT7_AR_OSLMT_OFFSET 24
#define CFG_SCHE_PORT6_AR_OSLMT_LEN    8
#define CFG_SCHE_PORT6_AR_OSLMT_OFFSET 16
#define CFG_SCHE_PORT5_AR_OSLMT_LEN    8
#define CFG_SCHE_PORT5_AR_OSLMT_OFFSET 8
#define CFG_SCHE_PORT4_AR_OSLMT_LEN    8
#define CFG_SCHE_PORT4_AR_OSLMT_OFFSET 0

#define CFG_SCHE_PORT3_AW_OSLMT_LEN    8
#define CFG_SCHE_PORT3_AW_OSLMT_OFFSET 24
#define CFG_SCHE_PORT2_AW_OSLMT_LEN    8
#define CFG_SCHE_PORT2_AW_OSLMT_OFFSET 16
#define CFG_SCHE_PORT1_AW_OSLMT_LEN    8
#define CFG_SCHE_PORT1_AW_OSLMT_OFFSET 8
#define CFG_SCHE_PORT0_AW_OSLMT_LEN    8
#define CFG_SCHE_PORT0_AW_OSLMT_OFFSET 0

#define CFG_SCHE_PORT7_AW_OSLMT_LEN    8
#define CFG_SCHE_PORT7_AW_OSLMT_OFFSET 24
#define CFG_SCHE_PORT6_AW_OSLMT_LEN    8
#define CFG_SCHE_PORT6_AW_OSLMT_OFFSET 16
#define CFG_SCHE_PORT5_AW_OSLMT_LEN    8
#define CFG_SCHE_PORT5_AW_OSLMT_OFFSET 8
#define CFG_SCHE_PORT4_AW_OSLMT_LEN    8
#define CFG_SCHE_PORT4_AW_OSLMT_OFFSET 0

#define CFG_SCHE_PORT7_AW_PRIVCFG_LEN    2
#define CFG_SCHE_PORT7_AW_PRIVCFG_OFFSET 30
#define CFG_SCHE_PORT6_AW_PRIVCFG_LEN    2
#define CFG_SCHE_PORT6_AW_PRIVCFG_OFFSET 28
#define CFG_SCHE_PORT5_AW_PRIVCFG_LEN    2
#define CFG_SCHE_PORT5_AW_PRIVCFG_OFFSET 26
#define CFG_SCHE_PORT4_AW_PRIVCFG_LEN    2
#define CFG_SCHE_PORT4_AW_PRIVCFG_OFFSET 24
#define CFG_SCHE_PORT3_AW_PRIVCFG_LEN    2
#define CFG_SCHE_PORT3_AW_PRIVCFG_OFFSET 22
#define CFG_SCHE_PORT2_AW_PRIVCFG_LEN    2
#define CFG_SCHE_PORT2_AW_PRIVCFG_OFFSET 20
#define CFG_SCHE_PORT1_AW_PRIVCFG_LEN    2
#define CFG_SCHE_PORT1_AW_PRIVCFG_OFFSET 18
#define CFG_SCHE_PORT0_AW_PRIVCFG_LEN    2
#define CFG_SCHE_PORT0_AW_PRIVCFG_OFFSET 16
#define CFG_SCHE_PORT7_AR_PRIVCFG_LEN    2
#define CFG_SCHE_PORT7_AR_PRIVCFG_OFFSET 14
#define CFG_SCHE_PORT6_AR_PRIVCFG_LEN    2
#define CFG_SCHE_PORT6_AR_PRIVCFG_OFFSET 12
#define CFG_SCHE_PORT5_AR_PRIVCFG_LEN    2
#define CFG_SCHE_PORT5_AR_PRIVCFG_OFFSET 10
#define CFG_SCHE_PORT4_AR_PRIVCFG_LEN    2
#define CFG_SCHE_PORT4_AR_PRIVCFG_OFFSET 8
#define CFG_SCHE_PORT3_AR_PRIVCFG_LEN    2
#define CFG_SCHE_PORT3_AR_PRIVCFG_OFFSET 6
#define CFG_SCHE_PORT2_AR_PRIVCFG_LEN    2
#define CFG_SCHE_PORT2_AR_PRIVCFG_OFFSET 4
#define CFG_SCHE_PORT1_AR_PRIVCFG_LEN    2
#define CFG_SCHE_PORT1_AR_PRIVCFG_OFFSET 2
#define CFG_SCHE_PORT0_AR_PRIVCFG_LEN    2
#define CFG_SCHE_PORT0_AR_PRIVCFG_OFFSET 0

#define CFG_SCHE_PORT7_AW_INSTCFG_LEN    2
#define CFG_SCHE_PORT7_AW_INSTCFG_OFFSET 30
#define CFG_SCHE_PORT6_AW_INSTCFG_LEN    2
#define CFG_SCHE_PORT6_AW_INSTCFG_OFFSET 28
#define CFG_SCHE_PORT5_AW_INSTCFG_LEN    2
#define CFG_SCHE_PORT5_AW_INSTCFG_OFFSET 26
#define CFG_SCHE_PORT4_AW_INSTCFG_LEN    2
#define CFG_SCHE_PORT4_AW_INSTCFG_OFFSET 24
#define CFG_SCHE_PORT3_AW_INSTCFG_LEN    2
#define CFG_SCHE_PORT3_AW_INSTCFG_OFFSET 22
#define CFG_SCHE_PORT2_AW_INSTCFG_LEN    2
#define CFG_SCHE_PORT2_AW_INSTCFG_OFFSET 20
#define CFG_SCHE_PORT1_AW_INSTCFG_LEN    2
#define CFG_SCHE_PORT1_AW_INSTCFG_OFFSET 18
#define CFG_SCHE_PORT0_AW_INSTCFG_LEN    2
#define CFG_SCHE_PORT0_AW_INSTCFG_OFFSET 16
#define CFG_SCHE_PORT7_AR_INSTCFG_LEN    2
#define CFG_SCHE_PORT7_AR_INSTCFG_OFFSET 14
#define CFG_SCHE_PORT6_AR_INSTCFG_LEN    2
#define CFG_SCHE_PORT6_AR_INSTCFG_OFFSET 12
#define CFG_SCHE_PORT5_AR_INSTCFG_LEN    2
#define CFG_SCHE_PORT5_AR_INSTCFG_OFFSET 10
#define CFG_SCHE_PORT4_AR_INSTCFG_LEN    2
#define CFG_SCHE_PORT4_AR_INSTCFG_OFFSET 8
#define CFG_SCHE_PORT3_AR_INSTCFG_LEN    2
#define CFG_SCHE_PORT3_AR_INSTCFG_OFFSET 6
#define CFG_SCHE_PORT2_AR_INSTCFG_LEN    2
#define CFG_SCHE_PORT2_AR_INSTCFG_OFFSET 4
#define CFG_SCHE_PORT1_AR_INSTCFG_LEN    2
#define CFG_SCHE_PORT1_AR_INSTCFG_OFFSET 2
#define CFG_SCHE_PORT0_AR_INSTCFG_LEN    2
#define CFG_SCHE_PORT0_AR_INSTCFG_OFFSET 0

#define CFG_SCHE_SCHE_MAGIC_WORD_LEN    32
#define CFG_SCHE_SCHE_MAGIC_WORD_OFFSET 0

#define CFG_SCHE_SCH_ECO_CFG0_LEN    32
#define CFG_SCHE_SCH_ECO_CFG0_OFFSET 0

#define CFG_SCHE_SCH_ECO_CFG1_LEN    32
#define CFG_SCHE_SCH_ECO_CFG1_OFFSET 0

#define CFG_SCHE_SCH_ECO_CFG2_LEN    32
#define CFG_SCHE_SCH_ECO_CFG2_OFFSET 0

#define CFG_SCHE_SCH_ECO_CFG3_LEN    32
#define CFG_SCHE_SCH_ECO_CFG3_OFFSET 0

#define CFG_SCHE_SCHE_VERSION_LEN    32
#define CFG_SCHE_SCHE_VERSION_OFFSET 0

#define CFG_SCHE_RESERVED_0_LEN    32
#define CFG_SCHE_RESERVED_0_OFFSET 0

#define CFG_SCHE_RESERVED_0_LEN    32
#define CFG_SCHE_RESERVED_0_OFFSET 0

#define CFG_SCHE_RESERVED_0_LEN    32
#define CFG_SCHE_RESERVED_0_OFFSET 0

#define CFG_SCHE_RESERVED_0_LEN      29
#define CFG_SCHE_RESERVED_0_OFFSET   3
#define CFG_SCHE_SCHE_BUSY_ST_LEN    3
#define CFG_SCHE_SCHE_BUSY_ST_OFFSET 0

#define CFG_SCHE_RESERVED_0_LEN         31
#define CFG_SCHE_RESERVED_0_OFFSET      1
#define CFG_SCHE_SCHE_DFX_ICG_EN_LEN    1
#define CFG_SCHE_SCHE_DFX_ICG_EN_OFFSET 0

#define CFG_SCHE_PORT3_AR_OSCNT_LEN    8
#define CFG_SCHE_PORT3_AR_OSCNT_OFFSET 24
#define CFG_SCHE_PORT2_AR_OSCNT_LEN    8
#define CFG_SCHE_PORT2_AR_OSCNT_OFFSET 16
#define CFG_SCHE_PORT1_AR_OSCNT_LEN    8
#define CFG_SCHE_PORT1_AR_OSCNT_OFFSET 8
#define CFG_SCHE_PORT0_AR_OSCNT_LEN    8
#define CFG_SCHE_PORT0_AR_OSCNT_OFFSET 0

#define CFG_SCHE_PORT7_AR_OSCNT_LEN    8
#define CFG_SCHE_PORT7_AR_OSCNT_OFFSET 24
#define CFG_SCHE_PORT6_AR_OSCNT_LEN    8
#define CFG_SCHE_PORT6_AR_OSCNT_OFFSET 16
#define CFG_SCHE_PORT5_AR_OSCNT_LEN    8
#define CFG_SCHE_PORT5_AR_OSCNT_OFFSET 8
#define CFG_SCHE_PORT4_AR_OSCNT_LEN    8
#define CFG_SCHE_PORT4_AR_OSCNT_OFFSET 0

#define CFG_SCHE_PORT3_AW_OSCNT_LEN    8
#define CFG_SCHE_PORT3_AW_OSCNT_OFFSET 24
#define CFG_SCHE_PORT2_AW_OSCNT_LEN    8
#define CFG_SCHE_PORT2_AW_OSCNT_OFFSET 16
#define CFG_SCHE_PORT1_AW_OSCNT_LEN    8
#define CFG_SCHE_PORT1_AW_OSCNT_OFFSET 8
#define CFG_SCHE_PORT0_AW_OSCNT_LEN    8
#define CFG_SCHE_PORT0_AW_OSCNT_OFFSET 0

#define CFG_SCHE_PORT7_AW_OSCNT_LEN    8
#define CFG_SCHE_PORT7_AW_OSCNT_OFFSET 24
#define CFG_SCHE_PORT6_AW_OSCNT_LEN    8
#define CFG_SCHE_PORT6_AW_OSCNT_OFFSET 16
#define CFG_SCHE_PORT5_AW_OSCNT_LEN    8
#define CFG_SCHE_PORT5_AW_OSCNT_OFFSET 8
#define CFG_SCHE_PORT4_AW_OSCNT_LEN    8
#define CFG_SCHE_PORT4_AW_OSCNT_OFFSET 0

#define CFG_SCHE_RESERVED_0_LEN               28
#define CFG_SCHE_RESERVED_0_OFFSET            4
#define CFG_SCHE_SLAVE_PORT_AR_CNT_CFG_LEN    3
#define CFG_SCHE_SLAVE_PORT_AR_CNT_CFG_OFFSET 1
#define CFG_SCHE_SLAVE_PORT_AR_CNT_EN_LEN     1
#define CFG_SCHE_SLAVE_PORT_AR_CNT_EN_OFFSET  0

#define CFG_SCHE_RESERVED_0_LEN               28
#define CFG_SCHE_RESERVED_0_OFFSET            4
#define CFG_SCHE_SLAVE_PORT_AW_CNT_CFG_LEN    3
#define CFG_SCHE_SLAVE_PORT_AW_CNT_CFG_OFFSET 1
#define CFG_SCHE_SLAVE_PORT_AW_CNT_EN_LEN     1
#define CFG_SCHE_SLAVE_PORT_AW_CNT_EN_OFFSET  0

#define CFG_SCHE_SCH_AR_TRANS_CNT_L_LEN    32
#define CFG_SCHE_SCH_AR_TRANS_CNT_L_OFFSET 0

#define CFG_SCHE_SCH_AR_TRANS_CNT_H_LEN    32
#define CFG_SCHE_SCH_AR_TRANS_CNT_H_OFFSET 0

#define CFG_SCHE_SCH_AR_FAIL_CNT_L_LEN    32
#define CFG_SCHE_SCH_AR_FAIL_CNT_L_OFFSET 0

#define CFG_SCHE_SCH_AR_FAIL_CNT_H_LEN    32
#define CFG_SCHE_SCH_AR_FAIL_CNT_H_OFFSET 0

#define CFG_SCHE_SCH_AR_BUS_BLOCK_CNT_L_LEN    32
#define CFG_SCHE_SCH_AR_BUS_BLOCK_CNT_L_OFFSET 0

#define CFG_SCHE_SCH_AR_BUS_BLOCK_CNT_H_LEN    32
#define CFG_SCHE_SCH_AR_BUS_BLOCK_CNT_H_OFFSET 0

#define CFG_SCHE_SCH_AR_SPLIT_TRANS_CNT_L_LEN    32
#define CFG_SCHE_SCH_AR_SPLIT_TRANS_CNT_L_OFFSET 0

#define CFG_SCHE_SCH_AR_SPLIT_TRANS_CNT_H_LEN    32
#define CFG_SCHE_SCH_AR_SPLIT_TRANS_CNT_H_OFFSET 0

#define CFG_SCHE_SCH_AW_TRANS_CNT_L_LEN    32
#define CFG_SCHE_SCH_AW_TRANS_CNT_L_OFFSET 0

#define CFG_SCHE_SCH_AW_TRANS_CNT_H_LEN    32
#define CFG_SCHE_SCH_AW_TRANS_CNT_H_OFFSET 0

#define CFG_SCHE_SCH_AW_FAIL_CNT_L_LEN    32
#define CFG_SCHE_SCH_AW_FAIL_CNT_L_OFFSET 0

#define CFG_SCHE_SCH_AW_FAIL_CNT_H_LEN    32
#define CFG_SCHE_SCH_AW_FAIL_CNT_H_OFFSET 0

#define CFG_SCHE_SCH_AW_BUS_BLOCK_CNT_L_LEN    32
#define CFG_SCHE_SCH_AW_BUS_BLOCK_CNT_L_OFFSET 0

#define CFG_SCHE_SCH_AW_BUS_BLOCK_CNT_H_LEN    32
#define CFG_SCHE_SCH_AW_BUS_BLOCK_CNT_H_OFFSET 0

#define CFG_SCHE_SCH_AW_SPLIT_TRANS_CNT_L_LEN    32
#define CFG_SCHE_SCH_AW_SPLIT_TRANS_CNT_L_OFFSET 0

#define CFG_SCHE_SCH_AW_SPLIT_TRANS_CNT_H_LEN    32
#define CFG_SCHE_SCH_AW_SPLIT_TRANS_CNT_H_OFFSET 0

#define CFG_SCHE_RESERVED_0_LEN        30
#define CFG_SCHE_RESERVED_0_OFFSET     2
#define CFG_SCHE_FUNC_SWITCH_RD_LEN    1
#define CFG_SCHE_FUNC_SWITCH_RD_OFFSET 1
#define CFG_SCHE_FUNC_SWITCH_WR_LEN    1
#define CFG_SCHE_FUNC_SWITCH_WR_OFFSET 0

#define CFG_SCHE_SCH_NS_CFG_EN15_LEN    2
#define CFG_SCHE_SCH_NS_CFG_EN15_OFFSET 30
#define CFG_SCHE_SCH_NS_CFG_EN14_LEN    2
#define CFG_SCHE_SCH_NS_CFG_EN14_OFFSET 28
#define CFG_SCHE_SCH_NS_CFG_EN13_LEN    2
#define CFG_SCHE_SCH_NS_CFG_EN13_OFFSET 26
#define CFG_SCHE_SCH_NS_CFG_EN12_LEN    2
#define CFG_SCHE_SCH_NS_CFG_EN12_OFFSET 24
#define CFG_SCHE_SCH_NS_CFG_EN11_LEN    2
#define CFG_SCHE_SCH_NS_CFG_EN11_OFFSET 22
#define CFG_SCHE_SCH_NS_CFG_EN10_LEN    2
#define CFG_SCHE_SCH_NS_CFG_EN10_OFFSET 20
#define CFG_SCHE_SCH_NS_CFG_EN9_LEN     2
#define CFG_SCHE_SCH_NS_CFG_EN9_OFFSET  18
#define CFG_SCHE_SCH_NS_CFG_EN8_LEN     2
#define CFG_SCHE_SCH_NS_CFG_EN8_OFFSET  16
#define CFG_SCHE_SCH_NS_CFG_EN7_LEN     2
#define CFG_SCHE_SCH_NS_CFG_EN7_OFFSET  14
#define CFG_SCHE_SCH_NS_CFG_EN6_LEN     2
#define CFG_SCHE_SCH_NS_CFG_EN6_OFFSET  12
#define CFG_SCHE_SCH_NS_CFG_EN5_LEN     2
#define CFG_SCHE_SCH_NS_CFG_EN5_OFFSET  10
#define CFG_SCHE_SCH_NS_CFG_EN4_LEN     2
#define CFG_SCHE_SCH_NS_CFG_EN4_OFFSET  8
#define CFG_SCHE_SCH_NS_CFG_EN3_LEN     2
#define CFG_SCHE_SCH_NS_CFG_EN3_OFFSET  6
#define CFG_SCHE_SCH_NS_CFG_EN2_LEN     2
#define CFG_SCHE_SCH_NS_CFG_EN2_OFFSET  4
#define CFG_SCHE_SCH_NS_CFG_EN1_LEN     2
#define CFG_SCHE_SCH_NS_CFG_EN1_OFFSET  2
#define CFG_SCHE_SCH_NS_CFG_EN0_LEN     2
#define CFG_SCHE_SCH_NS_CFG_EN0_OFFSET  0

#define CFG_SCHE_SCH_AW_CMD_CNT_L_LEN    32
#define CFG_SCHE_SCH_AW_CMD_CNT_L_OFFSET 0

#define CFG_SCHE_SCH_AW_CMD_CNT_H_LEN    32
#define CFG_SCHE_SCH_AW_CMD_CNT_H_OFFSET 0

#define CFG_SCHE_SCH_AR_CMD_CNT_L_LEN    32
#define CFG_SCHE_SCH_AR_CMD_CNT_L_OFFSET 0

#define CFG_SCHE_SCH_AR_CMD_CNT_H_LEN    32
#define CFG_SCHE_SCH_AR_CMD_CNT_H_OFFSET 0

#define CFG_SCHE_SCH_AW_RDY_CNT_L_LEN    32
#define CFG_SCHE_SCH_AW_RDY_CNT_L_OFFSET 0

#define CFG_SCHE_SCH_AW_RDY_CNT_H_LEN    32
#define CFG_SCHE_SCH_AW_RDY_CNT_H_OFFSET 0

#define CFG_SCHE_SCH_AR_RDY_CNT_L_LEN    32
#define CFG_SCHE_SCH_AR_RDY_CNT_L_OFFSET 0

#define CFG_SCHE_SCH_AR_RDY_CNT_H_LEN    32
#define CFG_SCHE_SCH_AR_RDY_CNT_H_OFFSET 0

#endif // __CFG_SCHE_REG_OFFSET_FIELD_H__
